• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The subject of the invention is a method of manufacturing a heterostructure comprising at least one elementary active photonic structure of III-V material on the surface of a silicon-based substrate comprising: - The production of a first pattern having at least a first opening (Oi1) and a first epitaxy operation of at least one III-V material; - the production of a second pattern with at least a second opening (Oi2) and a second epitaxy operation so as to produce the active photonic elementary structure having an external face; - An operation of transfer and assembly of the active photonic elementary structure via its external face, on an interface (300), said interface being produced on the surface of a second silicon-based substrate (301).
    公开号:FR3075461A1
    申请号:FR1762569
    申请日:2017-12-20
    公开日:2019-06-21
    发明作者:Fabrice Nemouchi；Charles Baudot；Yann Bogumilowicz；Elodie GHEGIN；Philippe Rodriguez
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Method for manufacturing a heterostructure comprising elementary photonic structures of lll-V material on the surface of a silicon-based substrate
    The field of the invention is that of components III-V and relates to a method for developing a structure for photonic applications, for example laser and more particularly of heterostructure of layer III-V on silicon substrate.
    The heterogeneous integration for example of an lll-V laser on an SOI substrate containing passive and active elements (waveguide, modulator, etc.) in silicon generally requires the transfer of chips of raw lll-V materials to an InP substrate which must then be cut and glued.
    Currently, this transfer according to the known art can be carried out according to different methods but in all cases uses the use of a substrate made of III-V material (generally an indium phosphide substrate) supporting the different epitaxial layers necessary for components in materials III-V.
    The main stages of production are:
    1) the production of III-V chips from a substrate for example of InP typically of 4 inches maximum on which a stack of III-V layer defining the characteristic layers of a laser or another device (photodetector ,. ..) have been epitaxied (the stacking of the epitaxial layers is reversed in order to stick in the right direction);
    2) then the transfer of these layers is carried out:
    - either collectively by having cut and placed chips on a support provided with an imprint commonly called a dedicated “holder”, in order to transfer them to the substrate;
    - Either individually by having previously cut the chips from 1 to a few square millimeters then by transferring and gluing each chip individually.
    In all cases, the chips of materials III-V are supported by an InP substrate whose initial diameter of the wafer is limited, requiring the removal of the support part (substrate In P) which represents approximately 98% of the thickness.
    Figures 1a to 1c illustrate the use of a carrier substrate called a "holder".
    More precisely, FIG. 1a illustrates the production of unitary housings etched in a substrate called holder 10, the production in parallel of at least one layer 21 of material III-V on the surface of a substrate 20 of material III-V and the cutting of elements 21 i / 20i designated by the term chip throughout this description and transferred to the “holder” 10 comprising elementary housings to receive each of the sets 21 i / 20i.
    FIG. 1b is an enlarged figure of a unitary assembly 21 i / 20i showing the possible misalignment margin d and the possible rotation of each of the chips during the transfer of a chip into a dedicated housing.
    FIG. 1c illustrates the collective transfer of all the chips (in the “holder”) to the surface, which then becomes the bonding interface 30, of an SOI-type substrate which may include passive and active elements (guide wave, modulator, ...) and metallization sets. Said interface being positioned on the surface of a support 31 called handle.
    It is necessary to have a handle because the receiving substrate has been previously thinned (on the rear face) of the entire silicon part serving as a support, the film a few μm thick containing the active and passive photonic elements, d '' a diameter of 300 mm, which cannot be handled without such a handle.
    The main issues encountered are as follows:
    - the need to manufacture the "holder", with costs and difficulties in reusing;
    - the placement of chips on the “holder” requiring cleavage of III-V plates with losses;
    - the long and tedious process of placing the chips;
    - the misalignment problem which can typically be 50 μm: plate to plate, from 100 to 150 μm: “holder” chips (collective transfer) with as constraint in the best case scenario: 300 pm plate chips (in the context of individual report);
    - the dismantling of the holder substrate resulting in the withdrawal of the III-V substrate (which generates a cost) with a lateral discount (no chemical selectivity);
    - variability (bonding rate of the chips and possible misalignment, plus potential rotation effect as illustrated in Figure 1b).
    FIG. 2 illustrates, the transfer and bonding of chips 20Î / 21Î individually produced after cutting a substrate 20 of material III-V and epitaxy of elements 21 of materials III-V and positioned on a plate comprising the substrate of the type SOI, comprising an interface 30, mounted on a support called handle 31.
    In this case the major issues are:
    - the need to cleave III-V plates (losses);
    - the placement of chips (long);
    - alignment accuracy: 50 pm plate to plate;
    - chip-to-chip variability;
    - disassembly of the substrate: with the removal of the III-V substrate (cost) and a lateral discount (no chemical selectivity);
    - variability: bonding rate of the chips and misalignment plus rotation.
    FIG. 3 illustrates in detail a basic photonic active structure produced in the invention, which can be of the laser type and recalls the characteristic dimensions of such a laser III-V. The multilayer stack III-V has a height typically of 2 to 5 μm in height and a width which can typically be between 40 and 90 μm in width. An Si guide is integrated in a layer of SiO 2 oxide produced on the surface of an Si substrate. FIG. 3 shows, the n-type contacts on a n-lnP base layer, a mesa structure comprising the stacking of the active region consisting of a quantum multi-well structure on which is stacked a p-lnP layer, a p-InGaAs layer and the p-type contact.
    In this context and to resolve the aforementioned drawbacks, the subject of the present invention is a method using a substrate commonly called a wafer, which may be of silicon or SOI as a growth substrate (or even identified as a donor substrate) in replacement of a substrate made of lll-V material (usually InP). The Applicant uses for this a technique described in particular in US Patent 8,173,551 and comprising the epitaxy of III-V material on a first silicon substrate, so as to preconstitute elementary substrates of III-V materials (and no longer d '' use massive substrates of materials III-V), on which active layers constituting for example a laser can be produced, before carrying out the transfer of the assembly onto a second substrate which may include passive and active elements (guide wave, modulator ...).
    The process of the invention has the following advantages in particular:
    - the use of a less expensive and easier to remove substrate;
    - the location of the epitaxial structures, so the structures can be reported collectively;
    - the use of elementary structures of the laser type in particular, which can be pre-aligned on a "donor" wafer, the alignment of the chips between them being at a precision related to lithography;
    - during the transfer, a single plate-to-plate alignment making it possible to obtain an accuracy in a range which can typically be from 10 μm to 80 μm with an average of 50 μm;
    - Obtaining a pre-encapsulation of the chips of III-V material in a dielectric.
    More specifically, the subject of the present invention is a method for manufacturing a heterostructure comprising at least one elementary active photonic structure comprising at least one active layer of III-V material on the surface of a silicon-based substrate comprising:
    - The production of a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate;
    - A first epitaxy operation of at least one lll-V material so as to define at least one elementary base layer of lll-V material in said at least first opening;
    - The production of a second pattern in a dielectric material so as to define at least a second opening having an overlap with said elementary base layer of III-V material;
    - A second epitaxy operation of at least one lll-V material on the surface of at least said elementary base layer of lll-V material so as to produce said at least photonic active elementary structure in material (x) lll -V having an external face;
    an operation of transferring and assembling said at least one photonic active elementary structure via its external face, on an interface which may include passive elements and / or active elements, said interface being produced on the surface of a second substrate to silicon base;
    - Removal of said first silicon-based substrate and said at least elementary base layer of III-V material located on said elementary photonic active structure.
    Advantageously, a chemical mechanical polishing operation (CMP) can be provided in order to remove any layers of non-active III-V materials located above the surface plane of the pattern and in order to obtain a bonding surface consisting of a single plan and meeting the bonding criteria (flatness, roughness, etc.), this operation being prior to the transfer and assembly operation.
    The substrate can typically be made of Si, SOI, Sii- x Ge x with 0 <x <1.
    According to variants of the invention, the production of said first motif comprises:
    - The production of at least one primary opening having at least a lower vertical part and an upper horizontal part, said vertical part being offset from said horizontal part;
    - the production of at least one elementary base layer comprising a lower vertical part and a horizontal part;
    the production of at least said elementary active photonic structure on the surface of the horizontal part of said elementary base layer of material III-V, in an offset manner relative to the lower vertical part of said at least elementary base layer in lll-V material.
    According to variants of the invention, the production of said first pattern comprises the production of at least one complex primary opening having at least:
    - a lower vertical part;
    - an intermediate horizontal part;
    - an upper vertical part;
    - said lower and upper vertical parts being offset in opposite manner with respect to said horizontal part;
    - Said first epitaxy operation defining at least one elementary base layer of primary III-V material having at least a lower vertical part and a horizontal part.
    According to variants of the invention, the method comprises for making said at least first complex opening:
    - The realization of said lower vertical part and said intermediate horizontal part;
    - depositing a sacrificial material in said lower vertical part and in said intermediate horizontal part so as to define at least one intermediate sacrificial element;
    - the deposition of an upper layer of dielectric;
    - The realization of at least said upper vertical part of said first opening in said upper dielectric layer so as to form at least said first complex opening;
    - the epitaxy of material III-V in said at least complex primary opening, so as to form said at least elementary base layer.
    The sacrificial material can advantageously be Sii- x Ge x with 0 <x <1 polycrystalline or amorphous. Advantageously, its removal can be carried out in a gaseous HCl and dihydrogen mixture at high temperature (typically> 500 ° C., the temperature chosen depending on the Ge concentration of said sacrificial layer).
    Advantageously, said assembly operation comprises a bonding operation, which can be a molecular bonding operation.
    The method according to the invention also advantageously makes it possible to produce different elementary structures which can operate at different wavelengths.
    This is why the present invention also relates to a method in which several different photonic active elementary structures are produced operating at different wavelengths.
    To do this, said method can comprise successive epitaxy operations for producing the various active elementary photonic structures, for example operating at different wavelengths, said operations being carried out successively at decreasing epitaxy temperatures.
    Advantageously, the interface has a support commonly known as a "handle" on a face opposite to said second substrate. The subject of the invention is therefore a method according to the invention in which said second silicon-based substrate is removed before assembly to leave it bare, the interface possibly comprising passive and / or active elements, said interface being on the surface of said support.
    According to variants of the invention, in order to produce active photonic elementary structures, structures with quantum multi-wells are advantageously made of material (x) III-V.
    According to variants of the invention, the elementary base layer of material III-V can advantageously be InP.
    The subject of the invention is also a heterostructure obtained according to the method of the invention, said heterostructure possibly advantageously comprising at least one structure of the laser or photodetector or modulator type.
    The subject of the invention is also a set of elementary active photonic structures made of III-V material on the surface of a silicon-based substrate obtained according to the method of the invention, which may advantageously include a set of laser structures operating at different wavelengths.
    The invention will be better understood and other advantages will appear on reading the description which follows given without limitation and thanks to the figures among which:
    - Figures 1 a to 1 c illustrate a first example of a method for transferring chips of material (x) III-V to an SOI substrate comprising the use of a "holder" according to known art;
    - Figure 2 illustrates a second example of a chip transfer process on an SOI substrate comprising the individual bonding of chips of material (x) III-V according to known art;
    - Figure 3 illustrates the typical dimensions of a laser type chip in III-V materials according to known art;
    - Figures 4a to 4f illustrate the main steps of a first example of a method according to the invention;
    - Figure 5 illustrates the different stages of a second example of a method of the invention comprising the production of a primary pattern having first complex openings making it possible to decentrate active photonic elementary structures relative to the elementary substrates made of III-V material ;
    - Figure 6 illustrates the transfer and assembly operation of the active photonic elementary structures obtained according to the operations described in Figure 5;
    - Figures 7a to 7d show top views and transverse views highlighting the dimensions of elementary active photonic structures in a method according to the invention;
    - Figure 8 illustrates an example of successive stages of manufacturing of different elementary structures according to the method of the invention;
    - Figure 9 illustrates a set of different photonic active elementary structures.
    The method of the invention makes use of the epitaxy method by trapping a crystal defect (linked to the difference in lattice parameter) making it possible to use a base substrate of semiconductor material such as silicon on which we first carry out elementary base layers of material III-V intended for the epitaxial growth of active photonic elementary structures such as for example quantum multi-well structures whose choice of the nature of the layers and their thicknesses determine the operating wavelengths.
    The elementary base layers of material III-V can be produced with high form factors making it possible advantageously to trap defects linked to the heterostructure. Growth techniques with high form factor have been described in particular in US Pat. No. 8,173,551.
    The process of the invention can be declined according to at least the following two alternatives and which are detailed in the following description:
    - first alternative: the method comprises two sequences of lithography and epitaxy of material (x) lll-V;
    - second alternative: the method comprises the manufacture of a particular pattern with the use of a sacrificial layer, in which an epitaxy operation of material (x) III-V is carried out.
    The Applicant describes below various examples of process according to the invention.
    Example of the process of the invention according to the first alternative:
    Figure 4a illustrates the following first steps:
    Step 1: a first low cost silicon substrate 100 is used.
    Step 2: from this first substrate 100, a dielectric layer 200 is produced.
    Step 3: Oü openings are made in the layer 200 so as to define a pattern with openings as illustrated in FIG. 4a. The square shows an enlarged view highlighting the type of flanks, straight or bevelled that can be obtained in the openings.
    Step 4: we carry out a first epitaxy operation of material III-V which may be of InP so as to define elementary base layers of material III-V: 201 i.
    FIG. 4b illustrates step 5: after having carried out a planarization operation of the CMP type (mechanical / chemical polishing), a second dielectric layer 200 is deposited in which second openings 0.2 are produced so as to define a second pattern.
    FIG. 4c illustrates step 6: a second epitaxy operation of material (x) III-V is carried out so as to define active photonic elementary structures 202i, then in step 7 there is an operation of planarization.
    The second openings have widths greater than those of the first openings so as to allow lateral growth of material (x) III-V from the substrates of materials III-V. The growth defects can advantageously be confined in the cavities (the dislocations are stopped by the walls of the cavity) of the substrates and make it possible to achieve growth of material (x) III-V from the substrates 201 i. Typically, from an Si substrate, the defects linked to the relaxation of the layers are mainly found in the crystal planes {111} forming an angle of 54.7 ° with the surface of the substrate. Therefore, if the height of the cavity O-h is greater than tan (54.7 °), the defects of these planes can be confined, typically, if the height is greater than 1.4 times the width of the cavity. The higher this ratio, the greater the containment effect.
    Figure 4d illustrates the second substrate used in the process of the invention. This substrate can be of the SOI type, which can include passive and active elements (waveguide, modulator, etc.) and sets of metallizations. It comprises a silicon part 301 and a part integrating the passive or active components 300 intended to address the elementary active photonic structure or structures produced on the surface of the first substrate 100, said second substrate being presented turned over (Step 8) to carry out the operation assembly.
    Step 9: For the purposes of the transfer, this second substrate is positioned on a support called handle 302 and the assembly operation is carried out with the elementary structure or structures produced in parallel, as illustrated in FIG. 4e. Typically, the assembly operation can be carried out using a molecular bonding operation.
    Step 10: the lower part 100 of the first substrate is removed as illustrated in FIG. 4f, exposing the elementary substrates 201 i by a mechanical thinning operation, then cleaning as illustrated in FIG. 4f.
    Step 11: finally, the part of the substrate comprising the dielectric 200 and the elementary base layers made of material III-V 201 i is removed, in order to release the active photonic elementary structures 202i as also illustrated in FIG. 4L
    Example of the process of the invention according to the second alternative:
    Advantageously, the elementary base layer made of IIIV material can be produced so as to comprise a first narrow vertical lower part capable of trapping growth defects from the first substrate and a wider upper horizontal part, said lower part being offset from said horizontal part, in order to be able to realize the growth of the active photonic elementary structure in a remote manner.
    FIG. 5 illustrates the different stages of this second example of a method:
    Step 1: a first low cost silicon substrate 100 is used.
    Step 2: from this first substrate 100, a dielectric layer 200 is produced.
    Step 3: Oü openings are made in the layer 200 so as to define a pattern with openings, having a vertical lower part and a horizontal part, said lower vertical part being off-centered with respect to said horizontal part. The square shows an enlarged view highlighting the type of flanks, straight or bevelled that can be obtained in the lower vertical part of the openings.
    Step 4: we proceed with the deposition of a sacrificial material so as to define elements 203i in the previously formed openings. A dielectric layer 200 is then deposited.
    Step 5: we just define in the dielectric layer 200, new openings constituting the upper vertical part of the first complex openings O’ü, by also removing the sacrificial material.
    The advantage of this first complex opening lies in the fact that the horizontal part is partially covered with dielectric making it possible to avoid a subsequent step of CMP type in order to standardize the surface of the elementary base layer made of lll-V material.
    Step 6: we carry out a first epitaxy operation of lll-V material making it possible to constitute the elementary base layers of lll-V 201 i material. The square highlights the remote aspect of the dislocations in the lower vertical part of the basic elementary layer with respect to the horizontal part of said basic elementary layer.
    Step 7: we proceed to make second openings (not shown) in which we carry out new epitaxy operations in order to produce the active photonic elementary structures 202i.
    The following steps for transferring the second substrate based on silicon and on active and / or passive components can be identical to those of the first example of the method previously described and are illustrated in FIG. 6 which illustrates the following steps:
    Step 8: the two substrates comprising on the one hand the elementary base layers of III-V material and on the other hand the support comprising an interface with active and / or passive components are assembled and bonded.
    Step 9: the part 100 of the first substrate is removed, exposing the elementary base layers of material III-V 201 i by a mechanical thinning operation.
    Step 10: finally, the part of the upper substrate comprising the dielectric 200 and the elementary base layers made of material III-V 201 i is removed to release the active photonic elementary structures 202i.
    Examples of dimensions of the elementary photonic active structures which can be produced according to the method of the invention are illustrated by means of FIGS. 7a to 7e.
    Typically, the first complex openings Ο’ι, may have surfaces of 50 to 100 μm x 500 μm.
    The thicknesses of the successive dielectric layers making it possible to define said first complex openings can be respectively 1 μm and 5 μm, as illustrated in FIG. 7a.
    FIG. 7b highlights the production of an elementary base layer of lll-V material of InP deposited by epitaxy in said complex opening. The thickness of InP can typically be between 5 to 10 μm with load effects between 5 and 10.
    In general, the loading effect corresponds to the difference in thickness observed when the same epitaxy process is carried out on (i) a substrate without patterns (ii) a substrate with pattern, i.e. partially covered by a pattern material such as SiO2.
    The thickness obtained is often greater in case (ii). The thickness ratio in case (ii) to thickness obtained in case (i) defines the load effect.
    In the present invention, an equivalent thickness of 5 to 10 μm on a substrate without pattern must make it possible to achieve lateral growth of 10 to 50 μm in the cavities in lateral growth on a substrate with pattern, therefore benefiting from the presence of the effect. dump.
    FIG. 7c highlights the production of a second opening in a conventional manner by photolithography.
    FIG. 7d highlights the epitaxial growth of the active photonic elementary structure of material (x) III-V, which may have a thickness typically between a few nanometers and a few microns depending on the intended applications.
    The method of the present invention makes it possible to sequence localized epitaxy operations, thus making it possible to produce different active photonic elementary structures, and in particular made up of different lll-V materials or different quantum multi-well structures, so as to manufacture within of the same set several different photonic functions that can operate at different wavelengths.
    FIG. 8 highlights the steps 7, 7bis, 7b and 7c corresponding to step 7 of the method described in FIG. 5 and relating to successive epitaxy steps allowing the formation of different elementary structures 202i, 202j, 202k from the elementary base layers of material III-V: 201 i, 201 j, 201k and by carrying out different masking operations. Step 7bis thus shows that after having carried out a first epitaxial growth operation to develop the elementary structure 202i, a masking operation intended for the epitaxial growth of the elementary structure 202j is carried out.
    FIG. 9 illustrates an example of configuration highlighting 4 different elementary active photonic structures 202i, 202j, 202k, 202I comprising quantum multi-wells between layers of materials III-V and assembled, at the level of silicon guide elements respectively 31 Oi, 31 Oj, 310k, 3101 produced in the substrate 300 comprising three dielectric levels of SiO 2 320, 321 and 322, the layer
    322 advantageously encapsulating the 4 active elementary photonic structures.
    It could also be different components (lasers, photodetector, lll-V modulator.
    According to the method of the invention, it is thus possible to produce, thanks to each of the epitaxy operations, an optimized component: laser / modulator / photodetector, with a size of the order of a few tens of microns.
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    1. A method for manufacturing a heterostructure comprising at least one elementary active photonic structure of lll-V material on the surface of a silicon-based substrate comprising:
    - The production of a first pattern having at least a first opening (Oh) in a dielectric material (200) on the surface of a first silicon-based substrate (100);
    - A first epitaxy operation of at least one lll-V material so as to define at least one elementary base layer of lll-V material (201 i) in said at least first opening;
    - The production of a second pattern in a dielectric material (200) so as to define at least one second opening (0.2) having an overlap with said at least elementary base layer of material III-V;
    a second epitaxy operation of at least one lll-V material on the surface of said at least elementary base layer of lll-V material so as to produce said at least photonic active elementary structure of material (x) lll- V having an external face;
    - An operation of transfer and assembly of said at least elementary active photonic structure via its external face, on an interface (300) which may include passive elements and / or active elements, said interface being produced on the surface of a second silicon-based substrate (301);
    - Removal of said first silicon-based substrate and said at least elementary base layer of III-V material located on said elementary photonic active structure.
    [2" id="c-fr-0002]
    2. Method according to claim 1, comprising a chemical mechanical polishing operation (CMP) prior to the transfer and assembly operation.
    [3" id="c-fr-0003]
    3. Method according to one of claims 1 or 2, wherein the production of said first pattern comprises:
    - The production of at least one primary opening having at least a lower vertical part and an upper horizontal part, said vertical part being offset from said horizontal part;
    - the production of at least one elementary base layer of lll-V material comprising a lower vertical part and a horizontal part;
    the production of at least said elementary active photonic structure on the surface of the horizontal part of said elementary base layer of material III-V, in an offset manner relative to the lower vertical part of said at least elementary base layer in lll-V material.
    [4" id="c-fr-0004]
    4. Method according to claim 3, in which the production of said first pattern comprises the production of at least one complex primary opening (Ο’π) having at least:
    - a lower vertical part;
    - an intermediate horizontal part;
    - an upper vertical part;
    - said lower and upper vertical parts being offset in opposite manner with respect to said horizontal part;
    - Said first epitaxy operation defining at least one elementary base layer of primary III-V material having at least a lower vertical part and a horizontal part.
    [5" id="c-fr-0005]
    5. Method according to claim 4, comprising:
    - The realization of said lower vertical part and said intermediate horizontal part;
    - depositing a sacrificial material in said lower vertical part and in said intermediate horizontal part so as to define at least one intermediate sacrificial element (203I);
    - the deposition of an upper dielectric layer (200);
    - making at least said upper vertical part of said first opening in said upper dielectric layer so as to form at least said first complex opening (0’1 i);
    - the epitaxy of material III-V in said at least complex primary opening, so as to form said at least said elementary base layer of material III-V (201 i).
    [6" id="c-fr-0006]
    6. The method of claim 5, wherein the sacrificial material is Sii- x Ge x with 0 <x <1, polycrystalline or amorphous.
    [7" id="c-fr-0007]
    7. The method of claim 6, wherein the removal of said sacrificial material is carried out in a gaseous HCl and dihydrogen mixture at a temperature above 500 ° C.
    [8" id="c-fr-0008]
    8. Method according to one of claims 1 to 6 wherein said assembly operation comprises a bonding operation.
    [9" id="c-fr-0009]
    9. The method of claim 8, wherein said bonding operation is a molecular bonding operation.
    [10" id="c-fr-0010]
    10. Method according to one of the preceding claims, in which several active elementary photonic structures (202i, 202j, 202k, 202I) are produced operating at different wavelengths.
    [11" id="c-fr-0011]
    11. Method according to the preceding claim, comprising successive epitaxy operations for producing the various active elementary photonic structures operating at different wavelengths, said operations being carried out successively at decreasing epitaxy temperatures.
    [12" id="c-fr-0012]
    12. Method according to one of the preceding claims, in which a support (303) is located on the face opposite to said second substrate, said method comprising removing said second substrate before assembly, to leave bare the interface which may include elements passive and / or active, said interface being on the surface of said support (303).
    [13" id="c-fr-0013]
    13. Method according to one of the preceding claims, in which the at least photonic active elementary structure (202i) comprises a quantum multi-well structure made of material (x) III-V.
    [14" id="c-fr-0014]
    14. Method according to one of the preceding claims wherein the at least elementary base layer of III-V material (201 i) is made of InP.
    [15" id="c-fr-0015]
    15. Heterostructure obtained according to the method of one of claims 1 to 14.
    [16" id="c-fr-0016]
    16. Heterostructure according to claim 15, characterized in that it comprises at least one laser or photodetector or modulator structure.
    [17" id="c-fr-0017]
    17. Heterostructure according to claim 16, characterized in that it comprises a set of laser structures operating at different wavelengths.
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    同族专利:
    公开号 | 公开日
    FR3075461B1|2020-02-14|
    EP3503223A1|2019-06-26|
    EP3503223B1|2021-04-07|
    US20190187375A1|2019-06-20|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US8173551B2|2006-09-07|2012-05-08|Taiwan Semiconductor Manufacturing Co., Ltd.|Defect reduction using aspect ratio trapping|
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    WO2017089676A1|2015-11-26|2017-06-01|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Illuminated faceplate and method for producing such an illuminated faceplate|
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    法律状态:
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    2019-06-21| PLSC| Publication of the preliminary search report|Effective date: 20190621 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 3 |
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    2021-12-31| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1762569|2017-12-20|
    FR1762569A|FR3075461B1|2017-12-20|2017-12-20|METHOD FOR MANUFACTURING A HETEROSTRUCTURE COMPRISING ELEMENTARY PHOTONIC STRUCTURES OF III-V MATERIAL ON THE SURFACE OF A SILICON-BASED SUBSTRATE|FR1762569A| FR3075461B1|2017-12-20|2017-12-20|METHOD FOR MANUFACTURING A HETEROSTRUCTURE COMPRISING ELEMENTARY PHOTONIC STRUCTURES OF III-V MATERIAL ON THE SURFACE OF A SILICON-BASED SUBSTRATE|
    EP18213610.1A| EP3503223B1|2017-12-20|2018-12-18|Method for manufacturing a heterostructure comprising iii-v material active or passive elementary structures on the surface of a substrate made of silicon|
    US16/226,470| US20190187375A1|2017-12-20|2018-12-19|Procede de fabrication d'une heterostructure comportant des structures elementaires actives ou passives en materiau iii-v a la surface d'un substrat a base de silicium|
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